1. Field of the Invention
The present invention relates to a display substrate and a display panel having the display substrate. More particularly, the present invention relates to a display substrate capable of decreasing gate signal delay, and a display panel having the display substrate.
2. Description of the Related Art
Generally, a liquid crystal display “LCD” panel includes an array substrate having a plurality of thin-film transistors “TFTs” and a plurality of pixel electrodes, a color filter substrate having a plurality of color filters and a common electrode, and a liquid crystal layer interposed between the array substrate and the color filter substrate. The array substrate further includes a plurality of gate lines and a plurality of data lines. The gate lines and the data lines are crossed with respect to each other to define a plurality of unit pixels. Each of the TFTs and the pixel electrodes are generally formed in the unit pixels.
The display quality of an image displayed on an LCD panel primarily depends on normal communication of signals applied to the gate lines and the data lines.
Particularly, as a display device becomes larger in size, the gate lines become longer such that the time constant associated with the gate lines is increased. Furthermore, as the resolution of an image increases, the required turn-on time of a TFT is relatively decreased. Therefore, when the time constant of the gate line is not sufficiently small, the gate signal delay is increased and thus the output of a gate integrated circuit “IC” is insufficient. As an LCD panel becomes larger in size and higher resolution images are required, gate signal delay may be further increased when the driving frequency thereof is increased from 60 Hz to 120 Hz for displaying an image.
When the resistance of the gate line is higher, the gate signal delay may be increased. Furthermore, when a parasitic capacitance of the gate line is higher, the gate signal delay may be increased. Therefore, in order to decrease the gate signal delay, research has focused on the usage of a low-resistance metal as the gate line material, resulting in a design that suppresses generation of the parasitic capacitance.
Recently, in order to enhance the side viewing angle of an LCD panel, a patterned vertical alignment “PVA” mode and a super PVA “SPVA” mode have been developed. In the PVA mode LCD panel, a pixel electrode is patterned so that a unit pixel area is divided into a plurality of domains. In the SPVA mode LCD panel, the patterned pixel electrodes are divided into a plurality of sub-pixel electrodes that are electrically isolated from each other. Particularly, when the sub-pixel electrodes formed in one unit pixel area are electrically connected to different gate lines, respectively, gate signal delay becomes an obstacle when an image is displayed on the SPVA mode LCD panel.